The prior art patent application Ser. No. 105,711, filed Dec. 20, 1979, now U.S. Pat. No. 4,354,228, by W. R. Kraft, et al, for "A Flexible Processor On A Single Semiconductor Substrate" of common assignee, the teachings of which are incorporated herein by reference, provides for the decoding of computer operation codes (OP codes) using a programmable logic array (PLA). (See page 11 of Kraft, et al.) A PLA typically includes an AND array and an OR array. Decoding of an OP code is done by applying the OP code to the AND array of the PLA, and by extracting the proper control information from the OR array of the PLA. When a sequence of control information is required for a given OP code, a clock signal is applied along with the OP code to the AND array, and a unique product line is provided in the AND array for each unique instruction time state resulting from each unique combination of OP code and clock signal (see page 5, lines 28-35, and page 15, lines 19-30 of Kraft, et al, supra). Because one instruction may have many such time states, and because there may be many instructions, a PLA is typically very large and slow for many applications.